High-Level Synthesis for Ultralow Power FPGAs
Davide Salusso
High-Level Synthesis for Ultralow Power FPGAs.
Rel. Mihai Teodor Lazarescu. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2020
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Abstract
The subject of this thesis is the capacitive sensors used in locating people indoors, especially in the health care of the elderly. This sensors have numerous advantages: cost, power, privacy and ease of installation while their main disadvantage is the steep loss of sensitivity by increasing the distance between the sensor and the person. To reduce the cost and installation complexity, the sensors are used in load mode, so only one plate of the capacity is needed because the other plate is the person's body along with the surrounding environment. In this thesis instead of processing the data on board the sensor with a micro-controller we used an ultralow-power FPGA like a hardware accelerator, and to process the data we use a neural network (NN) of the Multi-layer perceptron (MLP) type that have two hidden layers formed by eight neurons each and an output layer formed by a neuron.
It takes six 16-bit inputs and generates one output of four-bit
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