With the advance in silicon technology, recent electronic devices are becoming deeply embedded in extremely dense silicon dies and are required to comply with increasingly strict timing requirements. Under these circumstances, several faults can be induced by different causes, like defects in the manufacturing processes, process variations as well as ageing, workload, crosstalk and many other. Some of these defects can only be exposed by testing the delay characteristics of the circuit, so delay fault models are assuming a much more relevant position in fault analysis. However, delay fault models require much more computational effort with respect to simpler and more widespread fault models when producing the test.