The complexity of intergated circuits is increasing much faster than what CAD tools can handle. Even at IP level test cases can run for several hours or even days. Researchers and developers have introduced several techniques to tackle this issue. One promising ap- proach to speed-up the veri cation process is co-emulation. Before diving into details, this thesis gives a background on Universal Veri cation Method- ology (UVM) which allows Test-bench modularity and reusability. The available co- emulation techniques and their advantages and drawbacks are then discussed, with par- ticular focus on the one used in this research project: Test-bench acceleration.