When it comes to design a system, being it hardware or software, verification is a step of extraordinary relevance, especially when the conceived product is deployed into a safety critical application or in expensive production process. However, this procedure suffers from the demanding challenge of the quick-scaling computational complexity, which becomes of significant importance when referring to big-sized models. The aim of this dissertation is to highlight the state-of-the-art verification methodologies, along with their advantages and drawbacks, and to discuss one cutting-edge technique deployed into a real-life industrial context: The alteration of an existing C/C++ model to support a C-vs-RTL verification process, and the generation of an automated testing framework suitable for verifying the correctness of the changes.