Design of a clock diagnostic module for Built-In Self-Test of System on Chip

Anna Ferrara

Design of a clock diagnostic module for Built-In Self-Test of System on Chip.

Rel. Guido Masera. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2018

Abstract:	Design of test chip for SoC's electrical measurements using BIST (Built-In Self Test) mechanism, test bench developing, design simulation, synthesis, constraints definitions
Relators:	Guido Masera
Academic year:	2018/19
Publication type:	Electronic
Number of Pages:	66
Additional Information:	Tesi secretata. Fulltext non presente
Subjects:
Corso di laurea:	Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea:	New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici:	QT Technologies Ireland Limited
URI:	http://webthesis.biblio.polito.it/id/eprint/9807

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