Hardware acceleration for post-quantum cryptography
Flavio Tanese
Hardware acceleration for post-quantum cryptography.
Rel. Guido Masera, Maurizio Martina. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2018
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Abstract
Communication security of today heavily relies on the assumption that some mathematical problems are extremely difficult to solve and thus breaking encryptions based on such problems requires a very long time. While such encryptions are secure now, the probable diffusion of quantum computers in the foreseeable future makes the initial assumption fall short: quantum computations are efficient at breaking the most widespread algorithms in use. Post-quantum cryptographic systems are based on problems that are not (or marginally) affected by the peculiarity of quantum computing: AES and many other hashing functions fall in this category, with quantum operations just moving the problem from O(N) to O(sqrt(N)), with N being the number of operations needed to find a solution.
This is effectively countered by using double the number of bits and squaring the complexity
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