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Design and implementation of a hardware accelerator for Deep Convolutional Neural Networks

Osvaldo Genovese

Design and implementation of a hardware accelerator for Deep Convolutional Neural Networks.

Rel. Guido Masera, Maurizio Martina. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2018

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Abstract:
Relators: Guido Masera, Maurizio Martina
Academic year: 2018/19
Publication type: Electronic
Number of Pages: 63
Subjects:
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: UNSPECIFIED
URI: http://webthesis.biblio.polito.it/id/eprint/8468
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