Evelina Forno
Design of a parallel hardware architecture for Quantum Annealing Algorithm acceleration.
Rel. Andrea Acquaviva, Gianvito Urgese. Politecnico di Torino, Master of science program in Computer Engineering, 2018
|
Preview |
PDF (Tesi_di_laurea)
- Thesis
Licence: Creative Commons Attribution Non-commercial No Derivatives. Download (1MB) | Preview |
Abstract
Application acceleration on FPGAs
Relators
Academic year
Publication type
Number of Pages
Course of studies
Classe di laurea
Aziende collaboratrici
URI
 |
Modify record (reserved for operators) |
