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Instruction dispatch policy optimization for superscalar processors

Caracci, Fabio

Instruction dispatch policy optimization for superscalar processors.

Rel. Guido Masera. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2018

Abstract:

Instruction dispatch policy optimization for superscalar processors. On high performance CPUs implementing many different execution units, one problematic is making fast and good decision for incoming instructions steering to issue queues and execution units. Different parameters like execution units organization, data dependencies between instructions, instruction queues resource availability (…) should influence new instructions dispatch choice. The main goal of this work is studying and implementing various dispatch policies on a given high-end CPU in order to improve performance and simplify issue queues logic, within given timing constraints.

Relators: Guido Masera
Academic year: 2017/18
Publication type: Electronic
Number of Pages: 80
Additional Information: Tesi secretata. Full text non presente
Subjects:
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Ente in cotutela: EURECOM - Telecom Paris Tech (FRANCIA)
Aziende collaboratrici: ARM France SAS
URI: http://webthesis.biblio.polito.it/id/eprint/7548
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