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Development of hardware accelerators on FPGA for convolutional neural networks

Giulia Altamura

Development of hardware accelerators on FPGA for convolutional neural networks.

Rel. Mario Roberto Casu. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2018

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Abstract:

The aim of this thesis is to develop an architecture to accelerate the operation of convolution performed by neural networks. In particular it is to implement a matrix-matrix multiplication by executing the equation "C = A*B*alpha + C*beta".
Relators: Mario Roberto Casu
Academic year: 2017/18
Publication type: Electronic
Number of Pages: 72
Subjects:
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: UNSPECIFIED
URI: http://webthesis.biblio.polito.it/id/eprint/7457
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