Robert Margelli
System-level Design of a Latency-insensitive RISC-V Microprocessor and Optimization via High-level Synthesis.
Rel. Luciano Lavagno. Politecnico di Torino, Master of science program in Computer Engineering, 2017
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Abstract
System-level Design of a Latency-insensitive RISC-V Microprocessor and Optimization via High-level Synthesis
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