This thesis aims to develop an FPGA-based framework for accelerating matrix multiplication in attention mechanisms using High-Level Synthesis and the NN2FPGA workflow. The need for this work arises from the growing computational demands of lightweight object detection models such as YOLOv10n, where low latency and efficient use of hardware resources are essential. Existing software-oriented implementations are often not well suited to these constraints, which motivates the exploration of a hardware-based solution. To address this challenge, the ONNX network is quantized using symmetric power of two integer quantization to reduce computational complexity and improve hardware efficiency. A streaming-based computation approach is then adopted to organize the accelerator dataflow and support efficient execution on FPGA.