This thesis investigates datapath optimization strategies for low-precision floating-point computations, specifically FP8 and FP6 formats, targeted at Edge Artificial Intelligence (Edge AI) applications. Using Xilinx Vitis High-Level Synthesis (HLS), the research focuses on the design and comparative evaluation of Vector Multiply-Accumulate (MAC) architectures. To address the critical bottleneck of loop-carried dependencies in the accumulation stage, various architectural techniques, including loop pipelining, partial loop unrolling, and maximum unrolling combined with an explicit binary adder tree, are introduced. This work systematically evaluates and compares these different configurations to analyze their impact on hardware resource utilization, execution latency, and timing closure. By testing which optimization method provides the most timing-efficient solution, this study establishes a foundational framework for accelerating next-generation deep learning workloads on resource-constrained FPGA platforms..