Debugging modern System-on-Chip platforms based on the RISC-V architecture presents substantial challenges that grow in proportion to the system's architectural complexity. In a multi-master SoC such as X-HEEP, where a processor core and a DMA engine share access to multiple memory banks and peripheral interfaces through a pipelined OBI bus fabric, the root cause of a failure may lie not in the execution of a single instruction, but in the subtle interaction between concurrent bus transactions issued by independent masters. Furthermore, the internal bus activity of the SoC is inherently opaque to an external observer: without dedicated hardware support, there is no mechanism to inspect what is actually happening on the on-chip interconnect during execution.