Riccardo Fusari
Bus-Level Debug for RISC-V: A Hardware Sniffer and Automated Verification Framework for X-HEEP.
Rel. Maurizio Martina, Mariagrazia Graziano, Vincenzo Petrolo, Flavia Guella. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2026
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Abstract
Debugging modern System-on-Chip platforms based on the RISC-V architecture presents substantial challenges that grow in proportion to the system's architectural complexity. In a multi-master SoC such as X-HEEP, where a processor core and a DMA engine share access to multiple memory banks and peripheral interfaces through a pipelined OBI bus fabric, the root cause of a failure may lie not in the execution of a single instruction, but in the subtle interaction between concurrent bus transactions issued by independent masters. Furthermore, the internal bus activity of the SoC is inherently opaque to an external observer: without dedicated hardware support, there is no mechanism to inspect what is actually happening on the on-chip interconnect during execution.
This thesis presents a complete debug and verification framework for the X-HEEP RISC-V SoC, centered on a hardware Bus Sniffer module that is non-intrusive on the bus data path: it passively taps into ten OBI bus channels simultaneously without altering signal timing or arbitration outcomes, capturing transactions into 128-bit frames with cycle-resolution timing information, source identification, response latency, address, data, and control flags
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