Quantum computers are emerging as a revolutionary technology that exploits qubits, confined in one-dimensional quantum dots, to address complex problems that are currently beyond the reach of classical computers. In this work, a fully automated simulation framework was developed to investigate both the quantum dot confinement and transport behavior of custom designed semiconductor devices as host platforms for spin qubits, and subsequently simulate their fabrication using standard CMOS fabrication processes. The architecture considered is the planar MOS on a SOI wafer substrate, a highly mature design that can be fabricated through well-known processes extensively documented in the literature and remains feasible for manufacturing even for low-volume research laboratories.