Jacopo Cesaretti
Rapid Prototyping of Edge AI Accelerators: An HLS-based Approach for CNNs on FPGAs for the AIdge ML Deployment Framework.
Rel. Luciano Lavagno. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2025
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Abstract
The computational demands of modern Artificial Intelligence (AI), particularly for Convolutional Neural Networks (CNNs) in computer vision, are increasingly challenging to meet with traditional cloud-centric approaches. Relying solely on centralized cloud infrastructures introduces significant latency and bandwidth bottlenecks, while also raising concerns about data privacy and the substantial energy consumption of large-scale data centers. To overcome these limitations, the paradigm of edge computing has gained prominence, processing data locally on dedicated hardware. This work explores the deployment of CNNs on Field-Programmable Gate Arrays (FPGAs), reconfigurable devices that offer a compelling blend of parallel processing capability and energy efficiency for edge applications.
This thesis investigates a rapid prototyping methodology for FPGA-based CNN acceleration, leveraging the High-Level Synthesis (HLS) design flow
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