The growing deployment of batteryless Internet of Things (IoT) devices powered by ambient energy harvesting highlights the need for architectures capable of sustaining correct and reliable execution under frequent and unpredictable power interruptions. This thesis addresses this challenge by proposing RISE (RISC-V Intermittent System Extensions), an architectural and ISA-level framework that enables intermittent computing on a pipelined RISC-V processor. The proposed approach introduces four lightweight hardware modules: the Intermittent Computing Register Wrapper (ICRW), which encapsulates the processor state and tracks modifications through dirty-bit management; the Power Control Unit (PCU), which performs selective background backups of modified registers; the Restore Control Unit (RCU), which reloads saved state upon power resumption; and the Dispatcher, which transparently arbitrates memory bus usage between normal execution and backup transfers.