Giorgio Fardo
Fault Attack Injection strategies for RISC-V Microprocessors in Simulated Environments.
Rel. Alessandro Savino, Stefano Di Carlo. Politecnico di Torino, Corso di laurea magistrale in Cybersecurity, 2025
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Abstract
Hardware and software security are becoming increasingly critical due to the widespread proliferation of computing systems and the exponential growth of the IoT and embedded domains, both of which demand robust protection mechanisms. Addressing the rising sophistication and impact of attacks requires reducing the complexity of software testing against specific classes of vulnerabilities. In this context, access to simulator software capable of evaluating software robustness against such attacks can significantly lower the cost of security assessments and shorten the time to market of final products. This thesis presents modifications to the gem5 architectural simulator through the integration of a fault injection module for the RISC-V architecture.
The proposed module enables the injection of register level single and multi-bit faults during simulation, supporting both fine-grained, deterministic fault injection and general fault testing through randomized spatial and temporal fault distributions
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