This thesis explores the architectural evolution and verification methodologies associated with modern GPUs, with a particular focus on their role in high-performance and data-intensive applications. General purpose registers are integral to every digital design, thus ensuring reliable read and write functions is crucial. Transitioning from deprecated methodologies, like OVM, to contemporary methodologies, like UVM, aims to enhance efficacy, reduce manual effort, and improve scalability for future designs. The objective is to profile both current and previous methodologies to identify flow limitations and improve the register verification process through automation of design data capture and processing. This migration seeks to eliminate technical debt, ensure scalability, and increase overall efficiency.