Alessandro Vargiu
FPGA Acceleration in SmartNICs: Porting and Performance Evaluation of the Rosebud Framework.
Rel. Luciano Lavagno. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering), 2025
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Abstract
Field Programmable Gate Arrays (FPGAs) have emerged as a consolidated solution to address the challenges of high-performance networking applications, used in cloud computing environments, datacenters and telecommunication in general. The usage of FPGAs as accelerators for Smart Network Interface Cards (smartNICs) provides a flexible solution for tasks that require packet processing, such as deep packet inspection and firewalls. The inherent high performance and flexibility benefits of FPGAs are further improved by FPGA virtualization technology, which enables multi-tenancy execution through the distribution of FPGA resources, and by Partial Reconfiguration, which allows dynamic resource allocation and isolation, in order to optimize hardware utilization.
Today, several open-source solutions provide smartNIC functionalities to FPGAs, allowing the execution of tasks that are traditionally handled by CPUs to be offloaded to FPGA dedicated hardware accelerators
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