Francesco Marino
Exploration and Modeling of Logic in Memory Architectures Thesis Abstract.
Rel. Mariagrazia Graziano, Marco Vacca, Alessio Naclerio. Politecnico di Torino, Master of science program in Electronic Engineering, 2024
|
Preview |
PDF (Tesi_di_laurea)
- Thesis
Licence: Creative Commons Attribution Non-commercial No Derivatives. Download (6MB) | Preview |
Abstract
Modern CPU architectures are based on the Von Neumann model, which consists of two components: the processing unit and the memory unit. While the processing unit has significantly improved over time, memory capacity has not kept pace, leading to a substantial performance gap between the two, known as the "Memory Wall." The Memory Wall has been a subject of discussion for years, with one proposed solution being the "Logic in Memory" (LiM) paradigm. This approach involves embedding computational units within the memory to reduce memory access, power consumption, and data-fetching latency. Additionally, LiM-based architectures enable parallel computation, as each memory bank has its own independent computational unit(s).
To implement Logic in Memory architectures, emerging technologies such as resistive random-access memories (RRAMs), spin-transfer torque RAM (STT-RAMs), phase change memories (PCMs), and ferroelectric field-effect transistors (FeFETs) can be leveraged, as they offer advantageous features
Publication type
URI
![]() |
Modify record (reserved for operators) |
