Hierarchical Architecture of 2D-CNN Accelerator: Leveraging High-Level Design and Embedded Scalable Platfrom (ESP)
Angelina Marra
Hierarchical Architecture of 2D-CNN Accelerator: Leveraging High-Level Design and Embedded Scalable Platfrom (ESP).
Rel. Mario Roberto Casu, Luca Urbinati. Politecnico di Torino, Master of science program in Electronic Engineering, 2024
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Abstract
Starting from the existing sequential architecture of a 2D CNN accelerator, the hiercarchical architecture has been implemented, tested and deployed on a FPGA (profpga-xc7v2000t), leveraging High-Level Design and Embedded Scalable Platform (ESP).
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