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Hierarchical Architecture of 2D-CNN Accelerator: Leveraging High-Level Design and Embedded Scalable Platfrom (ESP)

Angelina Marra

Hierarchical Architecture of 2D-CNN Accelerator: Leveraging High-Level Design and Embedded Scalable Platfrom (ESP).

Rel. Mario Roberto Casu, Luca Urbinati. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2024

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Abstract:

Starting from the existing sequential architecture of a 2D CNN accelerator, the hiercarchical architecture has been implemented, tested and deployed on a FPGA (profpga-xc7v2000t), leveraging High-Level Design and Embedded Scalable Platform (ESP).

Relators: Mario Roberto Casu, Luca Urbinati
Academic year: 2024/25
Publication type: Electronic
Number of Pages: 80
Subjects:
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: UNSPECIFIED
URI: http://webthesis.biblio.polito.it/id/eprint/33065
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