Convolutional Neural Networks (CNNs) play a crucial role in image processing and computer vision. They are extensively used for tasks like image enhancement, filtering, and feature detection. Consequently, it is essential to efficiently implement convolution operations on hardware architectures to obtain superior performance when accelerating CNNs. The primary aim of this thesis is to explore different convolution implementations on Coarse-Grained Reconfigurable Arrays (CGRAs). CGRAs represent a departure from conventional computing architectures, offering enhanced flexibility and energy efficiency. In contrast to Application-Specific Integrated Circuits (ASICs), known for their efficiency but lack of flexibility, and Graphics Processing Units (GPUs), which are versatile but consume high power, CGRAs strike a balance by enabling instruction-level programming.