Davide Perticone
Development of a Software Interconnection for High-Level CPU Models Interoperability.
Rel. Luciano Lavagno. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering), 2023
Abstract: |
A microarchitectural model of a CPU system is a software used to simulate the internal structure and behavior of a CPU’s microarchitecture. They are used to simulate and predict the performance of a CPU under a variety of conditions, such as different workloads and clock frequencies. These models are complex and necessitate a significant amount of computational resources and technical expertise to develop, implement and maintain. When developing different CPU’s, it is of paramount importance that the related models ensure interoperability within each other. This allows reducing the development costs of new CPUs’ models as well as guaranting faster exploratory studies. The objective of this internship is to ensure the interoperability and connect two of the performance models maintained at Arm. This report will outline the motivation, the steps taken during the development process, and an analysis of the limitations of the previous connection. Additionally, the report will detail the newly created connection, including its capabilities and limitations. |
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Relators: | Luciano Lavagno |
Academic year: | 2022/23 |
Publication type: | Electronic |
Number of Pages: | 67 |
Additional Information: | Tesi secretata. Fulltext non presente |
Subjects: | |
Corso di laurea: | Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering) |
Classe di laurea: | New organization > Master science > LM-32 - COMPUTER SYSTEMS ENGINEERING |
Ente in cotutela: | INSTITUT EURECOM (FRANCIA) |
Aziende collaboratrici: | ARM France SAS |
URI: | http://webthesis.biblio.polito.it/id/eprint/26661 |
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