Pasquale Santoro
Implementation of a CNN hardware accelerator based on a reconfigurable spatial array.
Rel. Maurizio Martina, Guido Masera, Emanuele Valpreda. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2021
Abstract
Convolutional Neural Networks (CNNs) are currently the widely adopted approach to perform computer vision tasks with high accuracy. However, CNNs have a high computational complexity and a high amount of data movement. For this reason, their implementation on general purpose architectures makes not possible to meet latency and energy constraints. Instead, application specific integrated circuits represent an interesting choice for accelerating the filtering operation of the convolution. In this work, a dataflow-based architecture is implemented, which can be reconfigured to support the execution of different convolutional layers. The Spatial Array, based on the Output Stationary (OS) dataflow, performs the computations under different unrolling and interleaving degrees.
The Network on Chip (NOC) transfers data from the on-chip global buffer to the RFs of the array and vice versa, as instructions of an Instruction set architecture (ISA)
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