In the last years, the technological drivers that have underpinned the unceasing enhancement of processing systems performance are no longer sufficient to support the usual exponential trend. One of the main issues is linked to the standard Von Neumann organisation that is based on a clear division between the processing unit and the memory. This layout implies a constant data stream between CPU and data memory that are affected by a significant performance gap. The massive number of memory accesses results in power and latency overheads, further exacerbated in data-intensive applications. This thesis work presents the design of a novel architectural model that puts the spotlight on an alternative computing approach, i.e.