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Hardware Acceleration Based on FPGA for 5G NR Link Layer Simulator

Alberto Carboni

Hardware Acceleration Based on FPGA for 5G NR Link Layer Simulator.

Rel. Luciano Lavagno. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering), 2020

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Abstract:
Relators: Luciano Lavagno
Academic year: 2019/20
Publication type: Electronic
Number of Pages: 88
Subjects:
Corso di laurea: Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering)
Classe di laurea: New organization > Master science > LM-32 - COMPUTER SYSTEMS ENGINEERING
Aziende collaboratrici: TELECOM ITALIA spa
URI: http://webthesis.biblio.polito.it/id/eprint/14499
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