Erik Anzalone
Design and Implementation of efficient low power Hardware accelerators for Deep Learning Neural Networks.
Rel. Guido Masera, Maurizio Martina. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2019
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Abstract: |
Design and Implementation of efficient low power Hardware accelerators for Deep Learning Neural Networks |
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Relators: | Guido Masera, Maurizio Martina |
Academic year: | 2018/19 |
Publication type: | Electronic |
Number of Pages: | 103 |
Subjects: | |
Corso di laurea: | Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering) |
Classe di laurea: | New organization > Master science > LM-29 - ELECTRONIC ENGINEERING |
Aziende collaboratrici: | UNSPECIFIED |
URI: | http://webthesis.biblio.polito.it/id/eprint/10980 |
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