Advanced techniques for testing delay faults

One of the most used techniques for testing digital integrated circuits is functional test, above all during the operative lifetime(in-field test). In this specific case, functional test is performed on PULPINO processor, using an SBST(Software-Based Self-test) approach. On one hand, this kind of technique provides an effective way of testing without area or timing overheads, tipically introduced in DFT(design for testability) techniques; on the other hand, it gets difficulties in developing test programs. This master thesis aims to help the test engineer in developing the test program increasing the observability, in particular, of the transition delay faults, exploiting Modelsim and its functionalities because of the deep internal access the tool has on the DUT. A flow is created and validated on a simple circuit and then, applied to the processor concerned(PULPINO). The flow works on the Pulpino environment compiling the self-test(Assembly code test) and comparing the results generated by the golden simulation with the ones generated by each fault simulation corresponding to each signal of the fault list. If the two simulations are not equal it means that the fault changes the behaviour of the processor, so it is observable. The obtained results are relevant to the ones obtained using specific tools for testing, as Zoix and Tetramax.