Process Simulation and Compact Modelling for a Vertical Junctionless Nanowire Transistor

MOSFET have dominated the electronic industry for many years. However, the continuous dimensional scaling required to improve the integrated circuit’s performances and reduce the fabrication costs, gives rise to a series of issues. The most relevant one is the so-called Drain-Induced-Barrier- Lowering(DIBL), which consists in a loss of the gate’s control over the channel and results in an increase of the power consumption per chip. To overcome these issues, novel device architectures have been conceived. The most promising one is the Gate-All-Around(GAA) configuration. Moreover, as the gate length reaches the nanometer range, it becomes really challenging to precisely control the dopant atoms distribution and so to construct abrupt pn junctions. To this aim, the Junctionless Transistor (JNT) is an innovative device which does not rely on junctions and so greatly simplifies the fabrication process. In this work, the fabrication process of a Vertical JNT p type transistor is simulated by means of Synopsis Sentaurus Process, and the results of the electrical simulations performed with Synopsis Sentaurus Device are compared to the experimental data of measurements on devices fabricated at the Laboratory for Analysis and Architecture of Systems affiliated to the French National Centre for Scientific Research(LAAS-CNRS). The TCAD simulations have been tuned to obtain the experimental characteristic curves, by providing also some interesting physical insights on the functioning of the studied device. In the second part of the project, an analytical compact model of JNT, inherited from literature, has been implemented in MATLAB. The MATLAB compact model has been thus fitted and validated against the experimental data, considering three different nanowire diameters. In all the cases, an error lower than 10% is obtained. This is a good result, since 10% is considered as a threshold under which a result is considered reliable in industrial electronics. Finally, the compact model parameters have been tuned based on the Sentaurus results in order to fit the simulated transcharacteristic, thus obtaining a further validation of the compact model. This physical model could be integrated into a SPICE simulator so as to simulate complex digital circuits based on the technology under study and, based on the simulation results, optimize again the device parameters, thus speeding up the production.