Exploring the impact of RCQ approach in an unrolled LDPC decoder

This thesis addresses the implementation of a high-performance Low-Density Parity-Check (LDPC) code decoder, crucial for achieving Ultra Reliable Low Latency Communication (URLLC) as envisioned by the 3GPP consortium. Future technologies like the tactile internet, autonomous vehicles, and telemedicine require robust Forward Error Correction (FEC) methods, and LDPC codes are ideal due to their rapid convergence and reliability in noisy environments. However, high-throughput LDPC decoders often face challenges related to area efficiency and routing congestion. To overcome these limitations, this work introduces a fully reconfigurable, fully unrolled, and parallel LDPC decoder using the Reconstruction-Computation-Quantization (RCQ) paradigm. The architecture supports Offset-Min-Sum (OMS) and Min-Sum (MS) decoding algorithms, optimizing the use of fine-grain pipelining to achieve higher throughput. RCQ effectively reduces hardware area with minimal Frame Error Rate (FER) degradation, utilizing unique quantization parameters for each iteration. Implemented in 65 nm CMOS technology, the proposed architecture uses a (648,540)-LDPC code from IEEE 802.11n, applying 3-bit quantization for min-sum messages across ten iterations with three distinct RCQ parameter sets: one for initial LLR quantization and reconstruction, one for the first five iterations and one for the last five. The results demonstrate substantial improvements in both throughput and area efficiency compared to existing designs. This compact, high-throughput LDPC decoder provides a practical and scalable solution for next-generation communication systems, balancing performance and resource utilization to meet the stringent demands of modern multi-user scenarios.