From FinFET to Nanosheet Si-SiGe GAAFET: fabrication process simulation and analysis

The field-effect transistors are one of the building blocks of modern electronics. In the last 50 years, transistor technology had a noticeable development. According to Moore's law, the transistor dimensions became and continue to become very small: from the first MOSFET having a channel length of 20 um in 1960 to the actual multigate devices (FinFET and GAAFET) with a channel length of a few nanometers. This continuos race is due to the increasing demand in electronic systems, not only for high integration density, but also for high performance and low power consumption. In this context, this thesis aims to investigates, by means of physical simulations, multigates FETs. In particular, the work is divided into four parts. In the first part, the entire fabrication process of bulk FinFET is simulated in TCAD Sentaurus Process. Particular effort is spent in tuning each fabrication step to get a functional n-type and p-type transistor, from fins fabrication with Sidewall Image Transfer (SIT) until gate stack and contacts deposition processes; then, the previously simulated fabrication process is modified to simulate strained bulk FinFET by introducing the epitaxial growth of SiC and SiGe in the source and drain creation process step. The second part of the thesis consists on performing an electrical characterization of the two versions of the bulk FinFET by means of Sentaurus Device. For both types of FinFET is made a comparison between the case with and without stressed channel. Especially, it is underlined how the compressive (SiGe) and tensile (SiC) stress implies an increase in the mobility of the carriers and consequently in the ON current Ion and Subthreshold Swing (SS). In particular, it resulted an increment of about 20/30% in the Ion and an improvement of about 3% in the SS. In the third part, the effort spent in the bulk FinFET fabrication process is exploited to simulate the similar Gate-All-Around FET fabrication process. Indeed, several steps are inherited from FinFET process. The main difference are the realization of alternating layers of silicon and silicon germanium, the introduction of silicon nitride inner spacer, and the subsequent etching of SiGe layers. Also in this case the fabrication of non strained and SiC/SiGe strained version are simulated. In addition, beside bulk GAAFET, also the fabrication process of a Silicon-On-Insulator (SOI) GAAFET is simulated. And finally, in the last part of the thesis, the different versions are electrically characterized with Sentaurus Device and compared. Again an increment in the ON current is obtained in the comparison between non strained/strained channels and concerning the comparison between bulk and SOI version, an enhancement of Drain-Induced-Barrier Lowering (DIBL) is obtained. Throughout this thesis, process simulations are performed in Sentaurus Process, electrical characterization with sentaurus Device and results are visualized with Sentaurus Inspect and post-processed in MatLab or MS Excel. A brief tutorial on Sentaurus suite is presented at the end of the thesis. In conclusion, the purpose of this thesis is to provide the advantages and disadvantages among the different device versions simulated and to demonstrate why nowadays there is a fervent push in substitute FinFET with GAAFET devices.