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Thesis by Catanese, Antonino

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Antonino Catanese. Design and Development of a DSP Accelerators Array in a FPGA-based Clustered Architecture for Space Applications. Rel. Maurizio Zamboni. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2022

This list was generated on Sun May 19 04:59:38 2024 CEST.

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