Study and development of a new Fault Simulator for the new generation of European FPGA
Alessandro Di Chiara
Study and development of a new Fault Simulator for the new generation of European FPGA.
Rel. Luca Sterpone. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering), 2017
Abstract
Development of a new Fault Simulator for the New Generation of European FPGA
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