Modern integrated circuit design faces critical timing challenges during the Engineering Change Order (ECO) stage, where fixing hold timing violations often conflicts with setup timing requirements across multiple process corners. This conflict is particularly severe because a fix that resolves hold violations at one corner may degrade setup timing at another, making full automation difficult to achieve. Existing automated solutions, such as a Qualcomm® proprietary tool, provide partial coverage but frequently fail when hold fixes would compromise setup timing. The conventional approach employs a scenario reduction strategy in the second iteration, which increases fix rates but loses visibility into potential issues in excluded scenarios.