Modern processors increasingly rely on instruction-level parallelism to enhance execution speed. With the continuous miniaturization of silicon technology, it has become possible to design cores with very wide issue units; however, the degree of parallelism attainable through wider issue widths varies significantly across workloads and is ultimately constrained by inherent instruction dependencies. This work tries to explore methods of detecting which instructions act as the bottleneck for execution, and then presents some possible strategies to prioritize these critical instruction over others along a CPU's pipeline. The focus is on load instruction, as they typically are the highest latency instructions and offer multiple opportunities for optimization along the memory system.