Cross-Core Memory Validation using SBST Transparent Algorithms
Francesco Montagner
Cross-Core Memory Validation using SBST Transparent Algorithms.
Rel. Riccardo Cantoro, Matteo Sonza Reorda. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2025
Abstract
This work proposes and evaluates a runtime-configurable framework for RAM testing (SRAM/DRAM) in silicon validation, with a focus on transparent March tests that preserve user data. Starting from fault models and well known March U, the algorithm is refactored into a Transparent version, based on three phases: Signature Prediction (SP), Transparent March (TS), and an Additional Transparent March (AT March), while maintaining March U coverage with overall complexity O(35n). The Transparent algorithm is based on the evaluation and comparison of different signatures, that can be computed both in HW and in SW. One of the goals of this work is to estimate the impact of the SW signature computation proposing an efficient HW implementation.
The memory test environment developed supports multiple cores and bus hierarchies (e.g., ARM and RISC-V within the target SoC), enabling not only defect detection but also fault localization: by running the same test from different observation points, the method distinguishes memory-cell failures from failures along the access path
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