The thesis work focuses on the improvement of a RISC-V RV32IM-compatible core and, in particular, into the development of a custom standard-compatible extension to improve performance and power consumption. The target for the extension's design is an encryption algorithm. A work flow for design, testing and estimations of timing, area and power is provided leveraging on the following set of tools: - A Digilent Nexys DDR4 FPGA board for the implementation; - Desing Suite and Toolchains (Vivado, Visual Studio Code, GNU makefile, GCC); - Multiple languages for hardware descritpion, programming and scripting (systemverilog, VHDL, python, C, bash).