C-model based verification of a generic IP: an automatic UVM based approach for the functional verification of RTL designs through correspondence checking with a reference C??model
Andrea Amato
C-model based verification of a generic IP: an automatic UVM based approach for the functional verification of RTL designs through correspondence checking with a reference C??model.
Rel. Maurizio Martina. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2023
Abstract
Universal Verification Methodology (UVM) is a standardized methodology for verifying complex integrated circuit designs in the semiconductor industry. For the verification of some IPs it may be convenient to use a golden model, which generates the ideal expected outputs which are compared in scoreboard with the actual outputs of the design under test (DUT). Golden models are mostly written in C or C++ to reproduce the correct functionality of the DUT. IP verification with the help of high-level models is a frequent practice, because of its ease of implementation and speed of simulation as compared to doing the same at a lower level of abstraction (RTL).
In the current thesis is proposed an approach to efficiently verify the lower level RTL and determine its correspondence with the C model
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