With ever-increasing design complexity, versatility, and ubiquity, pre-silicon hardware design verification, and bug localization has become the critical bottleneck and the most time-consuming part of the design cycle, often taking 70% of available resources. While checking behavior compliance is one side of the verification coin, the other side entails finding "what went wrong?'', in other words, the root causing the bug. Debugging functional bugs in contemporary hardware designs often takes weeks due to the hundreds of thousands of lines of design source code and several GB of simulation trace data, thereby challenging design productivity and time-to-market. To ease that pain point, in this dissertation, we propose VeriBug, a deep learning-based automated bug localization framework identifying suspicious portions in hardware design source code responsible for design failure.