Antonio Colonna
Optimization of NS-GAAFET technology through low-κ dielectrics for spacer fabrication.
Rel. Gianluca Piccinini, Fabrizio Mo, Chiara Elfi Spano. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2023
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Abstract
Over the years, the manufacturing technology and structure of transistors has had continuous development. The channel length dimension has steadily decreased and the number of transistors per chip has steadily increased. With the scaling and the considerable increase in the number of transistors, problems related to power consumption, transistor speed, interconnection delays and the achievement of channel lengths of a few nanometers problems such as the short channel effect (SCE) have had to be faced. If the technological breakthrough of the last decade is represented by the Finfet which has made it possible to solve many problems thanks to the use of a 3D technology, the next step is represented by the GAAFET, Gate All Around Field Effect Transistor.
GAAFET technology with greater electrostatic control allowed scaling beyond 5 nm
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