Flash memories are non-volatile solid-state memories that can be electrically erased and programmed, based on an array of floating gate MOSFETs, thus able to retain information indefinitely, even when not powered. Thanks to good performances for read and write operations, embedded flash memories are widely adopted, especially in the System-on-Chip domain. Flash memories are characterized by a high storage density; thus, they can be affected by many possible faults, and they require complex and long test algorithms. The first part of this work is focused on the analysis of sequential read accesses performed by the CPU, called back-to-back readouts, and their timing verification.