Since the early 90s, almost every high-end microprocessor has been making use of out-of-order execution to exploit the instruction-level parallelism (ILP) a program exposes and execute the maximum number of operations at the same time. A big obstacle that hinders the performance of out-of-order machines is given by dependencies that intrinsically serialize the execution flow and nullify the advantages that come from parallelization. Many techniques have been developed in order to overcome these limitations: branch prediction is able to bypass control-flow dependencies and instruction scheduling does the same for data dependencies. However, memory dependencies are still an undergoing issue because they are associated with the “memory wall”: the memory subsystem, which is constantly becoming more and more a strong bottleneck in high-end microprocessors.