Most modern microprocessor architectures use virtual memory as an abstraction of physical memory to make programs position independent and isolated from each other. While effective, this technique brings a lot of execution overhead, since each memory access needs to be handled by a series of memory lookups, that are by themselves quite slow already. For this reason, a cache-like structure called Translation Lookaside Buffer (TLB) is employed to accelerate virtual-to-physical address translation. It is well known that TLBs have a big impact on system performance, and a great amount of research has already been performed in order to optimize their effectiveness.