The stage/thesis activity foresees a complete development cycle of a PC-side SW interface that allows ECU SW update via CAN bus. This SW interacts with an AUTOSAR inspired Flash Bootloader (FBL) that reside in the ECU and is compliant with ISO 14229 (UDS protocol). The candidate will start from a set of requirements, draw the SW architecture, write and debug the code and, finally, run the validation tests.