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A Hardware Dynamic Information Flow Tracking Architecture for Low-level Security on a RISC-V Core

Christian Palmiero

A Hardware Dynamic Information Flow Tracking Architecture for Low-level Security on a RISC-V Core.

Rel. Luciano Lavagno. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering), 2018

Abstract:

Implementation of a hardware dynamic information flow tracking (DIFT) architecture on a RISC-V core in order to detect and stop memory corruption attack patterns, such as buffer overflows and format strings.
Relators: Luciano Lavagno
Academic year: 2017/18
Publication type: Electronic
Number of Pages: 76
Additional Information: Tesi secretata. Full text non presente
Subjects:
Corso di laurea: Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering)
Classe di laurea: New organization > Master science > LM-32 - COMPUTER SYSTEMS ENGINEERING
Ente in cotutela: EURECOM - Telecom Paris Tech (FRANCIA)
Aziende collaboratrici: UNSPECIFIED
URI: http://webthesis.biblio.polito.it/id/eprint/7575
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