Davide Pala
Design and programming of a coprocessor for a RISC-V architecture.
Rel. Massimo Poncino. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering), 2017
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Abstract: |
Design and programming of a coprocessor for a RISC V architecture |
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Relators: | Massimo Poncino |
Academic year: | 2017/18 |
Publication type: | Electronic |
Number of Pages: | 99 |
Subjects: | |
Corso di laurea: | Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering) |
Classe di laurea: | New organization > Master science > LM-32 - COMPUTER SYSTEMS ENGINEERING |
Aziende collaboratrici: | CEA-Atomic Energy Commission |
URI: | http://webthesis.biblio.polito.it/id/eprint/6589 |
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