In the emerging fields of neuromorphic computing and in-memory computing, Analog-to-Digital Converters (ADCs) present a critical performance bottleneck, often consuming up to 80% of total system energy and occupying nearly 70% of the core chip area. Successive Approximation Register (SAR) ADCs are widely utilized in these domains; however, their performance is heavily bottlenecked by conventional resistive and capacitive Digital-to-Analog Converters (DACs). These traditional DACs are highly susceptible to fabrication mismatch, which severely degrades the ADC's resolution and efficiency. Mitigating these inaccuracies typically requires advanced, complex calibration techniques that further inflate area and power consumption. To address these limitations, this research proposes a Neuromorphic Data Converter (NDC) based on a loop-unrolled SAR ADC architecture.