The increasing complexity of Neural Network models, combined with the growing demand for their deployment on resource-constrained platforms, has intensified the need for efficient hardware design methodologies. Nowadays, FPGAs are a promising solution for accelerating NN inference at the edge, thanks to their high flexibility and power efficiency, thus representing a favorable trade-off between GPUs and ASICs. In this context, NN accelerators are commonly implemented by mapping the layers to optimized HLS/RTL representations that are then interconnected through a streaming architecture. A key challenge in this design paradigm lies in configuring the pipeline stages, particularly in determining the degree of input and output parallelism for each layer.