Technology scaling in advanced CMOS nodes has significantly increased the impact of leakage power on the total energy consumption of large-scale digital systems. In modern system-on-chip (SoC) designs comprising millions of instances, leakage has become a dominant contributor, particularly under low-activity operating conditions. Although contemporary physical design flows employ multi-threshold voltage (multi-Vt) optimization techniques to reduce static power after timing closure, the achievable leakage recovery is fundamentally limited by the amount and distribution of available positive slack across pipeline stages. In deeply pipelined and non-uniform architectures, slack is often unevenly distributed, constraining further high-threshold voltage (HVT) conversion during ECO stages. This work proposes a controlled clock skew methodology aimed at redistributing timing slack to enhance leakage power recovery through additional Vt swapping.